• Up to 8 independent T1 or E1 ports configurable as either all T1 or all E1 only
• Full-duplex connectivity
• Channelized and fractional T1/E1, clear channel E1 supported
• Up to 256 usable n x 64K, where n is 1 to 24 for T1 and 1 to 32 for E1
• Line-rate performance for all ports channelized to DS-0
• Integrated CSUs/DSUs
• Internal or network clocking selectable on each port
• Per-port, dual-color status LED
• Loopback capabilities:
• Local and remote loopback at the T1/E1 level
• Response to embedded loopback commands
• Insertion of loopback commands into transmitted signal
• N x DS-0 system-side loopback
• Bit-error-rate-testing (BERT) pattern generation and detection per channel (maximum of 6 T1/E1 at a time)
• Programmable pseudorandom pattern up to 32 bits long, including all 0s, all 1s, 211, 215, 220, 220 Quasi-Random Signal Sequence (QRSS), 223, alternating 0s and 1s, 1-in-8, and 3-in-24
• 32-bit error-count and bit-count registers
• Fully independent transmit and receive sections
• Detection of test patterns with bit error rates up to 10-2
• 24-hour history maintained for error statistics and failure counts, at 15-minute intervals
• 16- and 32-bit cyclic redundancy check (CRC); 16-bit default |
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